The continuing demand for more sophisticated mobile devices has encouraged manufacturers to enable handheld devices such as mobile phones to support multimedia streaming content. A key standard in this technology is the DVB-H standard, which can transmit digital television signals and Internet services. As handheld devices may experience reception problems in some environments, manufacturers have introduced an additional error correction scheme known as multi-protocol-encapsulation forward-error-correction (MPE-FEC).
Please refer to FIG. 1 and FIG. 2 together. FIG. 1 is a diagram of a first related art DVB-H system 100. The DVB-H system 100 comprises a tuner 110, a base-band receiver 120, a host sub-system 130, an embedded memory 140, a media player 150, and an external memory 160. FIG. 2 is a diagram of an MPE-FEC frame. The MPE-FEC frame is a matrix made up of 255 columns by 1024 rows (please note that the number of rows is flexible, and an MPE-FEC frame may have 256, 512, 768 or 1024 rows) where the first 191 columns comprise application data (an OSI Layer 3 datagram, also known as an IP datagram), and the last 64 columns contain Reed-Solomon (RS) code parity data. Data is received byte by byte in a vertical direction, so each column is built up before data of a next column is received. Each row holds an RS (255,191,64) codeword, where a 64 bytes syndrome can be derived from each codeword.
The forward error correction process takes place in four stages. Initially, once entire data of an MPE-FEC frame is received, 64-byte syndromes respectively corresponding to each codeword of the MPE-FEC frame will be generated. Next, error locations will be calculated, and error values associated with the respective error locations determined. Finally, utilizing the error locations, the error values will be added to corresponding data bytes in the MPE-FEC frame to complete the process of forward error correction.
In the DVB-H system 100, the tuner 110 receives a data stream, and the base-band receiver 120 converts the data stream to an MPEG-2 transport stream, extracts bytes of the MPE-FEC frame, and stores them in the embedded memory 140. Once all the bytes of the MPE-FEC frame are received, the base-band receiver 120 calculates the corresponding syndromes, and then utilizes the syndromes to calculate the error locations and error values (full RS decoding) or utilizes a CRC check to find erasure information (e.g. error locations), and determines the error values from the erasure information (half RS decoding). The error values are added to the MPE-FEC frame in the embedded memory 140 to correct errors, and the resultant IP datagrams sent to the host sub-system 130 for further processing. As the entire MPE-FEC frame must be stored in the embedded memory 130, a 2 Mbit memory is required for storing a 255 bytes×1024 MPE-FEC frame. As this memory is on-chip, the huge size creates problems such as increased die size and degraded yield rate.
In order to avoid the use of such a large embedded memory (e.g. an SRAM), other related art DVB-H systems do not include an embedded memory, and instead store the MPE-FEC frame in the external memory (e.g. a DRAM). Please refer to FIG. 3. FIG. 3 is a diagram of a second related art DVB-H system 300. The DVB-H system 300 comprises a tuner 310, a base-band receiver 320, a host sub-system 340, a media player 350, and an external memory 360. A data stream is received by the tuner 310, then converted to an MPEG-2 transport stream by the base-band receiver 320, and data bytes of an MPE-FEC frame are extracted and sent to the external memory 360. Once all the data bytes are received, each codeword in the MPE-FEC frame is extracted and sent to the base-band receiver 320 for RS decoding. As the error corrected codeword must then be sent back to the host sub-system 340, there is a bi-directional bus between the base-band receiver 320 and the host sub-system 340. Sending the entire MPE-FEC frame across the bus creates very heavy traffic. A greater disadvantage of this conventional method, however, is that all stages of the RS decoding process must be performed in an interleaved sequence, only enabling single byte access of the DRAM and therefore resulting in very inefficient DRAM bandwidth utilization due to a large proportion of overhead required for each DRAM access. The overhead is the clock cycles upfront specifying command, row address and column address before the actual data transaction cycles take place. A burst DRAM access is preferred since the proportion of overhead is much smaller than single byte access.